Nehalem Memory Speed Information

The memory controller in Intel's new Nehalem processor is a radical departure from previous Intel processor architectures, in that the processor die now contains a memory controller. As a result of this change, much of the system builder community is confused as to the proper memory speed to use for Nehalem processors.

This paper provides information to system builders so that the proper memory can be selected.

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This information is extracted from Intel documentation. It is correct, to the best of our knowledge, as of the time it was written.
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Overview

First Generation

The general high-level functional diagram of a first-generation Nehalem (Bloomfield & Gainstown) processor is:

The first-generation Nehalem processor architecture consists of either two or four Cores, and an UnCore. The UnCore consists of the Level-3 cache (including the controller and queue), the memory controller, and one or two QPI (Quick Path Interconnect) links. The UnCore is what will be discussed here, the memory controller in particular. This processor is targeted at high-performance desktop systems, workstations and servers.

The memory controller used in these Nehalem CPUs has three memory channels, each supporting up to three DDR3 DIMMs. This paper discusses the speed at which the DIMMs will run with various configurations.

All of the processors in this generation are specified by Intel as having 731 million transistors on a 263mm^2 die, using a 45nm process. The package size is 42.5mm x 45mm in an LGA-1366 form-factor.

Second Generation

Lynnfield

The general high-level functional diagram of the first of the second-generation Nehalem processors (Lynnfield) is:

The Lynnfield processor architecture consists of four Cores, and an UnCore. The UnCore consists of the Level-3 cache (including the controller and queue), the memory controller, the interface to 16 PCI-Express lanes (configurable as one x16 slot or two x8 slots) and a 2.5GT/S DMI (Direct Media Interface) link. This processor is targetted at mainstream desktop systems and uniprocessor servers.

The memory controller used in these Nehalem CPUs has two memory channels, each supporting up to three DDR3 DIMMs.

All of the Lynnfield processors are specified by Intel as having 774 million transistors on a 296mm^2 die, using a 45nm process. The package size is 37.5mm x 37.5mm in an LGA-1156 form-factor.

Clarksfield

The general high-level functional diagram of the second of the second-generation Nehalem processors (Clarksfield) is:

The Clarksfield processor architecture consists of four Cores, and an UnCore. The UnCore consists of the Level-3 cache (including the controller and queue), the memory controller, the interface to 16 PCI-Express lanes (configurable as one x16 slot or two x8 slots) and a 2.5GT/S DMI (Direct Media Interface) link. This processor is targetted for high-end laptop systems.

The memory controller used in this Nehalem CPU has two memory channels, each supporting one DDR3 SO-DIMM.

All of the Clarksfield processors are specified by Intel as having 774 million transistors on a 296mm^2 die, using a 45nm process. The package size is 37.5mm x 37.5mm in a PGA-988 form-factor.

Memory Information

The memory used by the Nehalem processors is DDR3. This is the third architectural generation of DDR (Double Data Rate) memory. It includes performance, power and density enhancements over both DDR and DDR2 memory. DDR memory (all generations) transfer data at double the clock rate. It does this by transfering data on both the rising and trailing edges of the clock.

There are three common ways to specify the clock speed of DDR3 memory. This table maps between the different specification methods for the memory speeds supported by the Nehalem CPUs:

JDEC Specification
DDR3 Speed
Memory Clock
PC3-6400
DDR3-800
400MHz
PC3-8500
DDR3-1066
533MHz
PC3-10666
DDR3-1333
666MHz

DDR3-1333 is sold specified at PC3-10600, PC3-10660 and PC3-10666. Any of these should be capable of functioning properly at the required speed.

In this paper, memory speed is specified by the Memory Clock.

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